A logic simulator is a software program or hardware device that emulates exactly how the logic it simulates will function. It is primarily used to verify the integrity of new designs, but can also be used to evaluate the performance of new and existing designs. The simulator of the present invention is a compiled two-valued rank-ordered boolean-level software type simulator, wherein program variables are used to represent boolean logic terms and program statements are used to evaluate the boolean equations of the design. Simulators of this type typically include a translator which can read the circuit boolean equations of the design and automatically generate the simulator program which, when executed on a computer, simulates the operation of the design.
For an illustration of the basic simulation method of the present invention, consider a "black box" logic device having eight inputs A-H and eight outputs (Y0-Y7). The logic desired is to assert one of eight outputs (Y0-Y7) depending on the state of eight input lines (A-H), such that input A has highest priority and input H has lowest. The function desired is specified in the following truth table:
__________________________________________________________________________ H G F E D C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 __________________________________________________________________________ X X X X X X X 1 1 0 0 0 0 0 0 0 X X X X X X 1 0 0 1 0 0 0 0 0 0 X X X X X 1 0 0 0 0 1 0 0 0 0 0 X X X X l 0 0 0 0 0 0 1 0 0 0 0 X X X 1 0 0 0 0 0 0 0 0 1 0 0 0 X X 1 0 0 0 0 0 0 0 0 0 0 1 0 0 X 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 __________________________________________________________________________
The truth table inputs in this example suggest a priority function, and the output suggests a decode function. One possible solution for this design objective is:
______________________________________ t = 0 A0 = A + b C + b d E + b d f G A1 = A + B + c d E + c d F A2 = A + B + C + D E0 = A + B + C + D + E + F + G + H t = 1 Y0 = A2 A1 A0 E0 Y1 = A2 A1 a0 E0 Y2 = A2 a1 A0 E0 Y3 = A2 a1 a0 E0 (lowercase terms are Y4 = a2 A1 A0 E0 complements of the Y5 = a2 A1 a0 E0 uppercase) Y6 = a2 a1 A0 E0 Y7 = a2 a1 a0 E0 ______________________________________
The Y0-Y7 equations are obviously a 3-to-8 decode of A0-A2 (along with enable term E0), but it is not obvious at first glance that A0-S2 represent an 8-to-3 priority encoder function of inputs A-H. Explained below is how a designer, using logic simulation, can be sure that A0-S2 along with E0 will create the Y-terms as required in the truth table.
The boolean logic set forth above can be simulated in a computer program by converting the boolean equations to corresponding computer program statements. To do so, program variables are used to represent variables in the boolean equations. For example, the variables L.sub.0, G1, G2, G3, G4, G5, G6, G7 and G8 can be assigned to represent the boolean variables A0, A, B, C, D, E, F, G and H, respectively. With these assignments, the boolean formula for A0 set forth above would be written as a FORTRAN statement as follows: EQU L.sub.0 =G1.or.(.n.G2.and.G3).or.(.n.G2.and.n.G4.and.G5) .or.(.n.G2.and.n..G4.and..n.G6.and.G7)
Similar statements can be written for the boolean equations for A1, A2, E0 and Y0-Y7 terms. The statements are then sequenced to form a logic simulation program that emulates the logic flow. Simulation can thus be carried out by defining the initial logical state of each variable in an input file (for example, A=1, B=1, C=0 . . . H=0) and executing the compiled simulator program. The program will thus output or determine a value for each of the Y0-Y7 terms based on the input data. This output can then be analyzed to see that the logic in fact operates as intended. Preferably, as noted above, a program is provided for automatically converting input boolean equations and wire tab files to a corresponding simulator program.
There are three distinct levels at which a designer may use a logic simulator in the design of a computer system. The first level consists of testing the logic of an IC design, as, for example, illustrated in the example above given. At times a small circuit can be quite tricky, and the simulator can help an engineer "one and zero it out", or verify its operation. The second level is testing at the multiple IC or module level. Inputs are specified in a special file, and outputs (or any boolean terms) can be monitored to see if they come out as expected. The last level of simulation involves assembling the new module(s) into a complete CPU simulator program to simulate the execution of instructions and diagnostics. At the first two levels of simulation, a designer may spend considerably more time analyzing the output than actually executing code, for deciding if the boolean worked correctly requires a rigorous digging through the output, boolean term by boolean term. At the CPU level, however, one need only check the pass and error counts to determine if a diagnostic passed or failed. If it failed, the diagnostic is run again and again while tracing relevant terms, much like probing on a real piece of hardware, or stepping through a program with a debugger to find software problems.
CPU simulation is a rigorous test of design correctness, where simulation occurs at the chip level all the way to user programs at the complete system level. Also, with multiple CPU systems it becomes increasingly important that the areas of the machine like the memory port and inter-CPU communications are thoroughly tested, which is best done at the system level. To accomplish this the simulator must be capable of simulating multiple CPUs all possibly "running" different programs.
The prior art provides at least two different ways to simulate multiple CPU systems. Since the boolean for one CPU is usually the same as any of the other CPU's, the simplest method re-generates the necessary simulation code for each CPU. If, for example, a simulator for one CPU uses 100000 lines of code this method requires N*100,000 lines of code (where N is the number of CPU's to simulate), and takes N times longer to execute than the simulation for one CPU would take. Another prior art method generates the code for one CPU but executes it N times. This eliminates the redundant code, but it still requires N times as much space for the variables to represent the boolean terms and takes N times as long to simulate. Accordingly, these prior art techniques become increasingly unworkable as the number of CPUs that need to be simulated increases. For instance, if it took two days worth of CPU time to simulate a single CPU simulation, a 16 processor system would take 32 days.